ZONG, Zhirui - HKUST Class Schedule & Quota

Class Schedule & Quota
2024-25 Summer 2024-25 Spring 2024-25 Fall 2021-22 Winter
2024-25 Spring
Common Core Course
The class information on this page will normally be updated every 15 to 20 minutes during class enrollment period.
» Student Information System (SIS)» PG Program/Course Catalog
Notes & Links
This service was first adapted from a student contribution in 2011-12 Fall. The efforts of all concerned are duly acknowledged.

AIAA AMAT BSBE CMAA DSAA EOAS FTEC FUNH INFH INTR IOTA IPEN LANG MICS PDEV PLED ROAS SEEN SMMG SOCH SYSH UCMP UCUG UFUG UGOD

COURSE INFO

VECTOR	[3-0-0:3]
DESCRIPTION	This course will focus on the integrated circuits for high-speed wireline data links. The topics that will be covered in this course include: wireline data link systems, drivers/transmitters, receivers, equalization techniques, clock-data recovery, etc.. Upon finishing this course, you are expected to understand the basic principles of modern high-speed data links and grasp the essentials to design the integrated circuits for such systems.

VECTOR

[3-0-0:3]

DESCRIPTION

This course will focus on the integrated circuits for high-speed wireline data links. The topics that will be covered in this course include: wireline data link systems, drivers/transmitters, receivers, equalization techniques, clock-data recovery, etc.. Upon finishing this course, you are expected to understand the basic principles of modern high-speed data links and grasp the essentials to design the integrated circuits for such systems.

MICS 6001R - Integrated Circuits for High-Speed Data Links (3 units)

Section	Date & Time	Room	Instructor	Quota	Enrol	Avail	Wait	Remarks
L01 (6286)	Mo 01:30PM - 04:20PM	Rm 201, W4	ZONG, Zhirui	20	5	15	0